Digital Logic - Programmable Logic Devices

Programmable Logic Devices (PLDs) are IC chips with internal logic gates connected by electronic fuses.
The fuses can be programmed to obtain different circuit configuration.

PLD(s) can be divide into 3 type of classes:-

        - Programmable Logic Array (PLA)
        - Field-Programmable Gate array
        - Programmable Array Logic

Programmable Logic Array (PLA)

-          a relatively small PLD that contains two levels of logic, where both levels are programmable

-           consider one of the most simplest device used in PLD

-          consist of regular arrangement of NOT, AND, and OR (gates)

         Each input have to pass through the NOT gates so that each input and it’s compliment are available                  
         to each AND gate. The output of each AND gate is available to each OR gate, and the output of each
         OR gate is the output of the chips

 a) Layout for 3-input and 2-output PLA

     b)  Programmed PLA

Field-Programmable Gate Array(FPGA)

The difficulty with increasing capacity of a strict SPLD architecture is that the structure of the programmable logic planes grows too quickly in size as the number of inputs is increased. The only feasible way to provide large capacity devices based on SPLD architectures is then to integrate multiple SPLDs onto a single chip and provide interconnect to programmably connect the SPLD blocks together. Most of the PLD product exist in the market are collectively referred to Complex PLDs (CPLDs) and the most important CPLD is FPGA

In FPGA contain an element called logic block. It is array of uncommitted circuit element.

The diagram above shows a simple logic block that consist of a D flip-flop, a 2-to-1 multiplexer, and a 16 bit lookup table. The lookup table is a memory that is consisting 16 1bit element, so that 4 lines input are required to select one of the 16 bits.

LIM ZERKIE 
 B031210127