1)Analysis of Combinational Circuits
Truth Table
Steps to create the truth
table :
Sample of combinational circuit
ⅰ. List all of the inputs found in the circuit, one input per
column.
a
|
b
|
c
|
d
|
|
ⅱ.Next, list the output.
a
|
b
|
c
|
d
|
y
|
ⅲ.Enumerate all possible combinations of the input
values. (For a circuit with n inputs,
there are 2n combinations)
a
|
b
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c
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d
|
y
|
0
|
0
|
0
|
0
|
|
0
|
0
|
0
|
1
|
|
0
|
0
|
1
|
0
|
|
0
|
1
|
0
|
0
|
|
1
|
0
|
0
|
0
|
|
1
|
1
|
0
|
0
|
|
0
|
1
|
1
|
0
|
|
0
|
0
|
1
|
1
|
|
1
|
0
|
0
|
1
|
|
0
|
1
|
0
|
1
|
|
1
|
0
|
1
|
0
|
|
1
|
1
|
1
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0
|
|
1
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1
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0
|
1
|
|
1
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0
|
1
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1
|
|
0
|
1
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1
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1
|
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1
|
1
|
1
|
1
|
ⅳ.Circuit annotated with the input
values abcd = 1101.
ⅴ.Complete truth table for the circuit.
a
|
b
|
c
|
d
|
y
|
0
|
0
|
0
|
0
|
1
|
0
|
0
|
0
|
1
|
1
|
0
|
0
|
1
|
0
|
1
|
0
|
1
|
0
|
0
|
1
|
1
|
0
|
0
|
0
|
1
|
1
|
1
|
0
|
0
|
0
|
0
|
1
|
1
|
0
|
1
|
0
|
0
|
1
|
1
|
0
|
1
|
0
|
0
|
1
|
1
|
0
|
1
|
0
|
1
|
1
|
1
|
0
|
1
|
0
|
1
|
1
|
1
|
1
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0
|
0
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1
|
1
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0
|
1
|
0
|
1
|
0
|
1
|
1
|
0
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0
|
1
|
1
|
1
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0
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1
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1
|
1
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1
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0
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Boolean Function
ⅰ.Write
down the Boolean logical expression at the output of each gate instead
of
substituting actual values of 0’s and 1’s for the inputs.
ⅱ.
From the diagram,we get the output y = (ab+cd)'.
ⅲ. Substitute
all possible combinations of values for all of the variables in
the
final equation, we should obtain the same truth table as before.
2)
Synthesis of Combinational Circuits
- A reverse procedure of the analysis of
combinational circuits
ⅰ.Start with a description of the operation of
the circuit.
ⅱ.
Derive either the truth table or the Boolean logical function that precisely
describes
the operation of the circuit.
ⅲ. Translate
that into a circuit diagram.
3) Technology
Mapping
- To reduce implementation cost and time to
produce a digital circuit on an IC,
off-the-
shelf semi-custom gate arrays is used.
- Many gate arrays are ICs that have only NAND
gates or NOR gates built in
them, but
their input and output connections are not yet connected.
- To use these gate arrays, connections
between the gates should be specified.
- convert all AND, OR, and NOT gates in the circuit
to use only NAND or NOR gates,
depending on what is available in the gate array.
- These NAND and NOR gates usually have the
same number of fixed inputs.
- Any combinational circuit can be constructed
with either only NAND gates or
only
NOR gates to make clear when we look at how these gates are built
at the transistor
level.
- The conversion of any given circuit to use
only 2-input NAND or 2-input NOR
gates
is possible by observing the following equalities which are obtained
from the Boolean
algebra theorems.
4) Minimization of Combinational
Circuits
Karnaugh Maps (K-map)
- The
K-map is a two-dimensional array of squares, each of which represents one
minterm in the Boolean
function.
- Thus, the map for an
n-variable function is an array with 2n squares.
- Labelling of two
adjacent columns or rows differ in only one bit change but for the
third and fourth rows are always
interchanged.
Using K-map to minimize a
4-variable function
1) To see how the
adjacencies involving one common term can appear,suppose we
have the logic equation below:
F = A’BC’D’+
A’BCD’ + AB’C’D’+ AB’CD +
ABCD’ +A’BC’D + AB’CD’ + A’B’CD
ⅰ.Since there are four variables in this equation, a
four variable K-Map is
used.
ⅱ. Encircle the largest number of “ones” that are a
power of two until all ones
are“covered”.
This means 2, 4 or 8 terms.
ⅲ.The reduced product terms are now determined by
observing the coverings. If the
variables under a covering
do not change they will be in the final minimized equation,
else they
are excluded.
For example, under the shaded covering, the
variables corresponding to A, B and C
do not change.Therefore that
term becomes ABC. The horizontal covering at the
bottom has
variables B, C and D do not change. Thus, that minimized term
becomes BCD.
ⅳ.The minimized equation is now written out by summing
the reduced product terms.
Thus the minimized
equation becomes:
F = AB’D’ + B’CD + BCD’ + A’BC’
KANG YI SHIN
B031210356
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